Data communication systems continue to require advanced methods of error detection of digital data being communicated over a noisy channel. In some cases when an error is detected, it is corrected, in other cases a retransmission of the data is needed
Cyclic redundancy check (CRC) codes have often been employed by digital communication systems to implement such error detection. CRCs may be calculated using a serial process, e.g., using an LFSR, in which single bits of a frame of data are accumulated one cycle at a time, to generate a frame check sequence (FCS) to be appended to the end of the data frame to be transmitted. The concatenation of the data frame with the FCS is designed to be exactly divisible by some predefined polynomial. Thus, if the original data frame to be transmitted is k bits long and the FCS is n bits long, then the total number of bits to be transmitted is k+n bits. The received k+n bits may then be divided by the predefined polynomial to insure that the division results in zero remainder. If a non-zero remainder does exist, however, then an error is detected between the bits received and the bits transmitted.
In order to accommodate large data frames, the CRCs may be expanded from the ability to handle single bits of data at each clock cycle, to the ability to handle multiple data bits, or words, in a single clock cycle. In order to generate CRCs for data words having widths greater than one bit, however, a different CRC circuit is required for each data word width that is to be processed.
In particular, communication protocols often utilize data packets having any number of data bytes. Given that each data byte represents 8 bits, for example, then performing CRC calculations on each data byte requires an 8-bit CRC circuit. Should CRC calculations be required on larger data blocks, however, a possibility exists that an un-processed data residue whose width is smaller than the current CRC handling width would need to be included in the current CRC calculation.
In such an instance, multiple CRC blocks having multiple widths would need to be incorporated into the design to handle the data residue widths that may be possible. For example, given a data block having a maximum width of 64 bits, CRC blocks having widths of 56, 48, 40, 32, 24, 16, and 8 bits would be necessary to handle the data residue widths that may result during CRC processing. Such a design could be size prohibitive.
Furthermore, other scenarios exist where data is received having varying widths, but real time CRC, processing on the variable width data blocks is still required. In such an instance, a first-in, first-out (FIFO) structure would be necessary to buffer the incoming data, but the possibility of varying data residue widths still remains.